The present invention relates to a method for manufacturing semiconductor structures of heterogeneous, non-heterogeneous or homogenous materials and in particular, for silicon containing or silicon-on-insulator (“SOI”) structures. The method includes thermally annealing a source-handle-structure by using first and second annealing steps. The first annealing step is stopped before detachment of the source substrate, and the second annealing step is then performed at a lower temperature than the first annealing step to prepare the source substrate for detachment of a useful layer at the predetermined detachment area.
Heterogeneous material compounds or structures such as heterostructures, particularly those consisting of a thin layer of a semiconductor material attached to a handle substrate, have attained considerable industry attention as the next generation of micro-device wafers, especially as used in the fields of microelectronics, optoelectronics or micromechanics.
In semiconductor technologies, thin layers are required which are only a few nanometers to a few micrometers thick with a very low thickness variance. Further, there is a major interest in monocrystalline thin layers. A very suitable technique to produce such thin films on a handle substrate is the SMART-CUT® process, offering a favorable way to produce for instance SOI (silicon on insulator) wafers with a high quality at low cost. One process flow to obtain SOI wafers using the SMART-CUT® process is shown schematically in FIGS. 6 and 7.
As shown in FIG. 6, two starting wafers, for instance a source or top silicon wafer 1′ and a handle or base silicon wafer 2′, are provided. An implantation of gaseous species like hydrogen and/or a rare gas such as helium is then executed to form a predetermined detachment zone 5′ at a certain depth d of the top silicon wafer 1′. Instead of an implantation, any other kind of process can be used which is able to introduce the gaseous species into the wafer 1′.
The predetermined detachment zone defines the location within the top wafer 1′ where detachment may occur. After implantation, the top wafer 1′ is divided in two regions: a thin region 3′ whose thickness is determined by the used implantation energy, and the remainder 4′ of the top wafer 1′.
In the next step, the thin region 3′ of the top wafer 1′ is bonded on its implanted surface to the base wafer 2′. Bonding is preferentially achieved by so-called direct wafer bonding based on molecular adhesion; however other bonding techniques such as a method with an intermediate glue layer, anodic bonding or a method with electrostatic treatment assistance can be used instead.
As shown in FIG. 7, the bonded wafer structure of the wafers 1′ and 2′ is then heated in a furnace 7 to supply energy to the bonded wafer structure, especially to the implanted wafer 1′ which includes detachment zone 5′ to weaken the structure. A fracture of the source wafer 1′ occurs after applying a certain energy to the wafer structure corresponding to a thermal detachment budget wherein a thermal budget is a certain quantity of energy fixed by two parameters: annealing time and annealing temperature. The fracture can be initiated not only thermally, but also by any form of additional energy brought to the wafer compound, such as mechanical energy or acoustic energy.
The thermal detachment budget is a certain thermal budget corresponding to the limit for thermal detaching or cleaving of a material, which is 100% of the necessary energy at which detachment occurs thermally. The temperature-time-dependency of the thermal detachment budget follows Arrhenius Law in which the reciprocal of the annealing time is proportional to the exponent of the reciprocal of the annealing temperature. The budget of thermal detachment of heterogeneous bonded structures is dependent on a number of material, environmental and technological parameters such as the type of material, implantation conditions and bonding conditions.
Then, the remainder 4′ of the top wafer 1′ can be detached resulting in a SOI-structure 8′ having the thin monocrystalline silicon layer 3′ transferred onto the silicon base wafer 2′.
According to the above example, both the top wafer 1′ and the base wafer 2′ are of silicon. When bonded and subsequently heated, almost no stress is created in the wafers.
Heterogeneous bonded structures such as SOQ (silicon on fused silica) compounds or other structures cannot be annealed at such high temperatures as silicon-oxide-silicon compounds to detach the semiconductor material. The difference between the thermal expansion coefficients of e.g. silicon and fused silica and the different temperature dependencies of the thermal expansion coefficients cause, especially during an annealing step, a high thermal stress in the structure.
In non-implanted bonded heterogeneous wafer compounds this stress leads either to an uncontrolled breakage of at least one of the two wafers and/or to a de-bonding of the wafers. When at least one wafer of the heterogeneous bonded wafer compound is implanted such as in the SMART-CUT® process, there is a sudden variation of stress in the heterogeneous wafer structure after the detachment of a remaining part of the implanted wafer when the detachment occurs at a temperature different from the bonding temperature. This can lead to an indefinite breakage of the wafer compound after such a detachment.
To solve this problem, the temperature of the thermal treatment of the heterogeneous wafer structure can be lowered. However, this lowering of temperature must be significant to avoid any indefinite breakage resulting in very long corresponding annealing times in order to achieve the thermal budget necessary for detachment of the implanted wafer. These annealing times are in the range of several days, and are therefore too long for commercial purposes.
Another solution, which has been presented for instance by Aspar et al in the Proceedings of MRS, 1998, uses a high dose hydrogen implantation to facilitate detachment of a wafer of a heterogeneous wafer compound at the implanted area. However, this high dose ion implantation is expensive.
U.S. Pat. No. 6,335,258 describes a method to transfer a thin layer to a heterostructure in which an implanted substrate is thinned down after bonding of this substrate with another substrate to limit a sudden stress variation during detachment of the compound. This method uses an additional processing step and results in significant material consumption because the removed material is lost.
U.S. Pat. No. 6,020,252 discloses a method to detach a structure at lower temperatures using a combination of a heat treatment and mechanical efforts such as traction, shearing or bending forces. Such forces can be applied with a tool a fluid or with another source of mechanical energy, for instance, with a jet as described in U.S. Pat. No. 6,427,748.
U.S. Pat. No. 5,877,070 suggests two specific methods of a SMART-CUT® process to lower a detachment temperature. The first method is based on an additional boron implantation step of the wafer. This method results in disadvantageous boron doping of the surrounding layers and, especially due to the additional implantation step for boron, is expensive and time-consuming. The second method which is of the above-mentioned type, uses pre-annealing before bonding of the wafers. However, the pre-annealing temperature is limited by the effect of blistering of the implanted wafer, resulting in a very fast formation of blisters at the surface of the wafer due to thermal treatment. Blistering occurs quickly with annealing and destroys the flatness of the wafer which is necessary for sufficient bonding of the wafer. After bonding, a second annealing step is done at a low temperature. Due to the limited thermal budget applied during the pre-annealing step, the second annealing step takes several days to reach the thermal budget to detach the implanted wafer.
There is a need for a method which can be easily practiced that has a reduced processing time and a very low risk of damage or destruction of the material while still achieving a high quality detached surface. The present invention now satisfies that need.